Routing (EDA)

Routing is a crucial step in the design of integrated circuits. It builds on a preceding step, called placement, which determines the location of each active element of an IC. Routing is then the process of adding all wires needed to properly connect all of the placed components while obeying all design rules.

The task of all routers is the same. They are given some pre-existing polygons consisting of pins (also called terminals) on cells, and optionally some pre-existing wiring called preroutes. Each of these polygons are associated with a net, usually by name or number. The primary task of the router is to create geometries such that all terminals assigned to the same net are connected, no terminals assigned to different nets are connected, and all design rules are obeyed. A router can fail by not connecting terminals that should be connected (an open), by mistakenly connecting two terminals that should not be connected (a short), or by creating a design rule violation. In addition, to correctly connect the nets, routers may also be expected to make sure the design meets timing, has no crosstalk problems, meets any metal density requirements, does not suffer from antenna effects, and so on. This long list of often conflicting objectives is what makes routing extremely difficult.

Almost every problem associated with routing is known to be intractable. The simplest routing problem, called the Steiner tree problem, of finding the shortest route for one net in one layer with no obstacles and no design rules is NP-hard if all angles are allowed and NP-complete if only horizontal and vertical wires are allowed. Variants of channel routing have also been shown to be NP-complete, as well as routing which reduces crosstalk, number of vias, and so on. Routers therefore seldom attempt to find an optimum result. Instead, almost all routing is based on heuristics which try to find a solution that is good enough.

Design rules sometimes vary considerably from layer to layer. For example, the allowed width and spacing on the lower layers may be four or more times smaller than the allowed widths and spacings on the upper layers. This introduces many additional complications not faced by routers for other applications such as printed circuit board or Multi-Chip Module design. Particular difficulties ensue if the rules are not simple multiples of each other, and when vias must traverse between layers with different rules.

Types of routers

The four main types of routers are:

• Maze router^[1]
• Line probe router^[2]
• Channel router^[3]
• Area routers

How routers work

Many routers execute the following overall algorithm:

• First, determine an approximate course for each net, often by routing on a coarse grid. This step is called global routing^[4], and may optionally include layer assignment. Global routing limits the size and complexity of the following detailed routing steps, which can be done grid square by grid square.

For detailed routing, the most common technique is rip-up and reroute:

• Select a sequence in which the nets are to be routed.
• Route each net in sequence
• If not all nets can be successfully routed, apply any of a variety of "cleanup" methods, in which selected routings are removed, the order of the remaining nets to be routed is changed, and the remaining routings are attempted again.

This process repeats until all nets are routed or the program (or user) gives up.

An alternative approach is to treat shorts, design rule violations, obstructions, etc. on a similar footing as excess wire length -- that is, as finite costs to be reduced (at first) rather than as absolutes to be avoided. This multi-pass "iterative-improvement" routing method^[5] is described by the following algorithm:

• For each of several iterative passes:
• Prescribe or adjust the weight parameters of an "objective function" (having a weight parameter value for each unit of excess wire length, and for each type of violation). E.g., for the first pass, excess wire length may typically be given a high cost, while design violations such as shorts, adjacency, etc. are given a low cost. In later passes, the relative ordering of costs is changed so that violations are high-cost, or may be prohibited absolutely.
• Select (or randomly choose) a sequence in which nets are to be routed during this pass.
• "Rip up" (if previously routed) and reroute each net in turn, so as to minimize the value of the objective function for that net. (Some of the routings will in general have shorts or other design violations.)
• Proceed to the next iterative pass until routing is complete and correct, is not further improved, or some other termination criterion is satisfied.

Most routers assign wiring layers to carry predominantly "x" or "y" directional wiring, though there have been routers which avoid or reduce the need for such assignment^[6]. There are advantages and disadvantages to each approach. Restricted directions make power supply design and the control of inter-layer crosstalk easier, but allowing arbitrary routes can reduce the need for vias and decrease the number of required wiring layers.

See also

• Electronic design automation
• Design flow (EDA)
• Integrated circuit design

Further reading

The external links in this article may not follow Wikipedia's content policies or guidelines. Please improve this article by removing excessive or inappropriate external links.

References

• Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field of electronic design automation. A portion of this summary was derived (with permission) from Chapter 8, volume II, Routing, by Lou Scheffer.

1. ^ C.Y. Lee (1961). "An algorithm for path connections and its applications". IRE Trans. Electronic Comput. EC-10. 
2. ^ D.W. Hightower (1969). "A solution to line-routing problems on the continuous plane". DAC’69: Proceedings of the 6th Annual Conference on Design Automation: 1-24, ACM Press. 
3. ^ J. Reed, A. Sangiovanni-Vincentelli, and M. Santamauro (1985). "A new symbolic channel router: YACR2". IEEE Trans. CAD: 203–219,. 
4. ^ J. Soukop (1979). "Global Router". Proceedings of the 16th Design Automation Conference: 481-489, San Diego, CA: IEEE Press. 
5. ^ F. Rubin (1974). "An iterative technique for printed wire routing". Proc. 11th Design Automation Workshop: 308-13. 
6. ^ R. Linsker (1984). "An iterative-improvement penalty-function-driven wire routing system". IBM J. Res. Develop 28 (5): 613–24.