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| INPUT A B |
OUTPUT A XOR B |
|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The XOR gate (sometimesEOR gate) is a digital logic gate that implements exclusive disjunction - it behaves according to the truth table to the right. A HIGH output (1) results if one, and only one, of the inputs to the gate is HIGH (1). If both inputs are LOW (0) or both are HIGH (1), a LOW output (0) results.
XOR gate is short for exclusive OR. This means that precisely one input must be 1 (true) for the output to be 1 (true). A way to remember XOR is "one or the other but not both."
This function is addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. A half adder consists of an XOR gate and an AND gate.
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Symbols
There are two symbols for XOR gates: the 'military' symbol and the 'rectangular' symbol. For more information see Logic Gate Symbols
A XOR B = A.(B') +(A').B, where A' represents NOT A.
Hardware description and pinout
XOR gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs. The standard 4000 series CMOS IC is the 4070, which includes four independent two-input XOR gates. The 4070 replaces the less reliable 4030, but keeps the pinout. The pinout diagram is as follows:
1 Input A1 2 Input B1 3 Output Q1 4 Output Q2 5 Input A2 6 Input B2 7 VG 8 Input A3 9 Input B3 10 Output Q3 11 Output Q4 12 Input A4 13 Input B4 14 VCC |
This device is available from most semiconductor manufacturers such as Philips. It is usually available in both through-hole DIL and SOIC format. Datasheets are readily available in most Datasheet Databases.
Alternatives
If no specific XOR gates are available, one can be made from four NAND or five NOR gates in the configurations shown below.
More than two inputs
The XOR operation is a binary operation and is therefore defined only for two inputs. [1] It is nevertheless common in electronic design to talk of "XORing" three or more signals.
The most common interpretation of this usage is that the first two signals are fed into an XOR gate, then the output of that gate is fed into a second XOR gate together with the third signal, and so on for any remaining signals. The result is a circuit that outputs a 1 when the number of 1s at its inputs is odd, and a 0 when the number of incoming 1s is even. This makes it practically useful as a parity generator or a modulo-2 adder.
See also
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